In flip chip processing of semiconductor integrated circuit (IC) chips, C4 solder bumps are used to connect IC dies to packaging. However, due to the coefficient of thermal expansion (CTE) mismatch between different layers in the packaging, C4 solder bumps experience large stresses which can lead to crack formation during chip joining. Testing has shown that a dielectric under the C4 bumps is more likely to crack during chip joining (referred to as “white bump formation”) when the effective modulus of the dielectric layers under the C4 bumps is lower. The effective modulus of the back end of line (BEOL) stack depends on the modulus of the dielectric layers in the stack and the amount and arrangement of the metallization in the stack. As the modulus of the metal features is typically much higher than that of the dielectric, the effective modulus of the stack can be increased by increasing the metal density.